1. Field of the Invention
The present invention relates to a semiconductor memory device such as Synchronous Dynamic Random Access Memory (SDRAM), and more particularly to a semiconductor memory device that is provided with capacitor fuses and to a method of checking the state of the capacitor fuses.
2. Description of the Related Art
Increases in the speeds of CPUs in recent years have been accompanied by demand for DRAM that can perform faster data reading and writing. SDRAM, which achieves higher operating speeds by operating in synchronization with clock signals from the outside, has come to be widely used as a means of achieving these higher data transfer speeds. SDRAM includes both SDR (Single Data Rate)-SDRAM, in which data are transferred only at the rising edge or the falling edge of a clock signal, and DDR (Double Data Rate)-SDRAM, in which a higher data transfer speed is achieved by transferring data at both the rising and falling edges of a clock signal. A DDR-II mode, which is a mode for higher-speed applications of DDR, is currently being investigated for achieving still higher speeds.
In this type of semiconductor memory device, fuse elements are used for operations such as storing the addresses of redundant memory cells and setting the parameters in initial micro-adjustment circuits. These fuse elements include types that normally function as resistor elements but that blow out and enter an insulating state when an over-current flows, and types that are cut by irradiation of a laser beam.
However, a certain amount of surface area is required to form resistor elements, and when this type of resistor element is used as a fuse element, there is the problem that an increase in the number of fuse elements results in a corresponding increase in the layout area. Capacitor fuses are therefore used to realize the fuse elements in limited areas. A capacitor fuse is an element in which the application of high voltage between two electrodes that are normally in an insulated state causes the destruction of a dielectric film, the resulting dielectric breakdown placing the two electrodes in a connected state. The use of this type of capacitor fuse allows one fuse element to be realized in the same layout area as one memory cell.
In contrast to a normal fuse element, which functions as a resistance element before being cut and then enters an open state after being cut, a capacitor fuse functions as a capacitor that is in an open state across the two electrodes before being cut and then functions as a resistor element after being cut.
In a semiconductor memory device that uses this type of capacitor fuse, the capacitor fuse must be checked for cutting when the power supply of the entire semiconductor memory device is turned on, the detection results being latched and taken as a determination result.
As one common method of checking the state of a capacitor fuse for detecting whether the capacitor fuse has been cut or not, a particular voltage is applied to the capacitor fuse, and then, after halting the application of this voltage, the voltage across the two ends of the capacitor fuse is measured. This method detects cutting of the capacitor fuse by taking advantage of the fact that the element will function as a capacitor and thus store the applied voltage if the capacitor fuse has not been cut, but will not store the applied voltage if the capacitor fuse has been cut.
This type of capacitor fuse is produced in the same fabrication step as memory cells and therefore has the same characteristics as memory cells. Normally, a voltage of 1.4 V is applied to one end of a memory cell while a voltage of 0.7 V is applied to the other end, whereby a voltage of only 0.7 V is applied across the two ends. In contrast, when detecting whether a capacitor fuse has been cut or not, a voltage of 1.4 V is applied to one electrode of the capacitor fuse while the other electrode remains at the ground (GND) voltage, and a voltage of 1.4 V is therefore applied across the two electrodes. In addition, this voltage of 1.4 V is applied to the capacitor fuse each time the power supply is supplied to the semiconductor memory device.
The voltage (super voltage: SVT) that is applied when cutting a capacitor fuse is normally 6-7 V, and the breakdown voltage of the capacitor fuse is therefore generally not set as high. Thus, increasing the applied voltage from 0.7 V to 1.4 V results in an exponential shortening of the life expectancy of the element. In other words, since the capacitor fuse is provided with the same characteristics as memory cells as previously explained, the application of a voltage to a capacitor fuse that is approximately twice the voltage that is applied to memory cells accelerates deterioration, and in a worst case, brings about the breakdown of the capacitor fuse. The breakdown of the capacitor fuse and the resulting conductive state of the capacitor fuse results in the problem of malfunctioning such as the alteration of the set specifications or difficulty in substituting defective memory cells with redundant memory cells.
However, if the voltage that is applied across the two electrodes of the capacitor fuse is simply made a voltage of 0.7 V, similar to the voltage in the memory cells, the occurrence of cutting in the capacitor fuse can no longer be detected.
As an example, an inverter of typical construction such as shown in FIG. 1 is used in a latch circuit unit for latching a determination signal based on the voltage that is stored in a capacitor fuse. This inverter is constructed from p-channel MOS transistor 81 and n-channel MOS transistor 82 and operates by inverting the logic of the voltage that is received as input from input terminal 80 and supplying the result as output from output terminal 83.
When a high-level voltage is received as input from input terminal 80 in this inverter, n-channel MOS transistor 82 turns on and p-channel MOS transistor 81 turns OFF, whereby the output terminal becomes low level, i.e., the GND potential. On the other hand, when a low-level voltage is received as input from input terminal 80, n-channel MOS transistor 82 turns OFF and p-channel MOS transistor 81 turns on, whereby high-level voltage VPERI is supplied to output terminal 83.
The operation of the inverter shown in FIG. 1 is next explained for a case in which voltage VPERI is 1.8 V and the high-level voltage that is received from input terminal 80 is 0.7 V.
When a voltage of 0.7 V is applied to input terminal 80, the voltage across the gate and source of n-channel MOS transistor 82 equals or exceeds the threshold value and the transistor turns on. However, the voltage across the source and gate of p-channel MOS transistor 81 is 1.1 V, and p-channel MOS transistor 81 therefore does not turn OFF. Essentially, p-channel MOS transistor 81 and n-channel MOS transistor 82 both turn on at the same time and the inversion operation is not performed correctly.
Accordingly, when detecting for the occurrence of cutting of a capacitor fuse, the voltage that is applied across the two ends of the capacitor fuse cannot be simply made 0.7 V, i.e., the voltage that is applied in memory cells. As a result, the voltage that is applied to a capacitor fuse when checking for the occurrence of cutting of the capacitor fuse is higher than the voltage that is applied to memory cells, and this higher voltage raises the problem of compromised reliability.
It is an object of the present invention to provide a semiconductor memory device in which the voltage that is applied to a capacitor fuse when checking for the occurrence of cutting in the capacitor fuse is made the same level as the voltage that is applied to memory cells, whereby an improvement in reliability can be obtained.
To achieve the above-described object, the semiconductor memory device of the present invention is provided with a power supply generation circuit unit and a capacitor fuse circuit unit.
The power supply generation circuit unit generates a first voltage and a second voltage that is lower than the first voltage. The capacitor fuse circuit unit is composed of a capacitor fuse, a circuit for charging the capacitor fuse with the first voltage, a sense amplifier for amplifying the difference in potential between the voltage that has accumulated in the capacitor fuse and the second voltage, and a latch circuit unit for latching the voltage level that has been amplified by the sense amplifier and supplying the result as a determination signal.
According to the present invention, when checking for the occurrence of cutting of a capacitor fuse, the capacitor fuse is charged with the first voltage, the difference in potential between the voltage that has accumulated in the capacitor fuse and the second voltage is amplified by the sense amplifier, and this amplified potential difference is then latched by the latch circuit unit and supplied as a determination signal. When the capacitor fuse has not been cut, the difference in potential between the first voltage and the second voltage is amplified by the sense amplifier, and when the capacitor fuse has been cut, the difference in potential between a voltage of substantially ground potential and the second voltage is amplified by the sense amplifier. As a result, a normal latch operation can be carried out in the latch circuit unit even when the first voltage is made a low voltage of the same level as the voltage that is normally applied to memory cells. The life expectancy of the capacitor fuse can therefore be raised to the same level as normal memory cells to obtain an improvement in the reliability of the semiconductor memory device.
In addition, the semiconductor memory device of the present invention may further be provided with a control unit for instructing the capacitor fuse circuit unit to charge the capacitor fuse with the first voltage upon detection of the supply of power, and for instructing the capacitor fuse circuit unit to perform the operations of halting charging of the capacitor fuse, amplifying by means of the sense amplifier, and latching the voltage level that has been amplified when an expansion mode register (EMRS) signal is received as input.
In addition, the semiconductor memory device of the present invention may further be provided with a control unit for: upon detection of supply of the power supply, instructing the capacitor fuse circuit unit to charge the capacitor fuse with the first voltage, and upon receiving a mode register (MRS) signal, instructing the capacitor fuse circuit unit to perform operations of: halting charging of the capacitor fuse, amplifying by means of the sense amplifier, and latching the amplified voltage levels.
Finally, the semiconductor memory device of the present invention may use, as the first voltage, a voltage that is half or less than half the power supply of the sense amplifier.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention.